The continual shrinking of integrated circuit device packing density has recently produced a dramatic new direction for semiconductor device manufacture. That new direction is the building of device structures in three dimensions in the substrate crystal. The practical building block for these new devices is a trench structure formed into the silicon substrate. New anisotropic etching techniques make it possible to form deep trenches with steep, nearly vertical, sidewalls. Various workers have proposed the formation of trench isolation regions and trench capacitors for memory cells. A more recent, and less well known, proposal is to form trench gate structures. The latter proposal, embodied in U.S. Pat. No. 4,455,740, issued June 26, 1984 to Hiroshi Iwai, was inspired by the desire to shrink MOS transistor dimensions, bringing the source and drain ever closer together. Iwai recognized that a point is reached where the source and drain are so closely spaced that punchthrough results. Accordingly, they teach a structure in which the source to drain spacing at the surface can be shrunk without regard to punchthrough by extending the gate length into the substrate, i.e. around the bottom of a trench, thereby physically separating the source and drain effectively in the vertical rather than the horizontal dimension. Improvements in that trench gate structure are embodied in U.S. patent application Ser. No. 674,855, Filed Nov. 26, 1984 (P. T. Panousis, Case 9).
It will be recognized that the foregoing proposal is essentially a technique for extending the length of the channel of an MOS device for a given surface area. Extending the length of the device decreases the operating speed of the device and decreases the gain of the device. These implications can be traded against the benefits just described and the trench gate structure, as envisioned by Iwai, may find significant device applications.
I have discovered a different trench gate device that resembles the Iwai device only in the respect that it employs a trench. In Iwai's device the trench is the gate of the device. In the device proposed here basically the entire device is built within the trench. That is, the source and drain regions also extend into the trench in order to realize all the benefits of my discovery. Primary among these is a substantial increase in the gain of the transistor for a given surface dimension. A host of new device structures are made possible using this approach.
The marriage of a trench capacitor with a trench gate is proposed in which an entire memory cell is formed essentially in the depth dimension of the substrate.